With the development of semiconductor manufacturing technology, to achieve a faster operation speed, a larger memory space and more functions, semiconductor chips are developed in a direction of high integration. As a result, the critical dimension of semiconductor devices becomes smaller continuously. Recently, in large scale integrated circuits, the critical dimension is already in the range from about several tens nanometers to about several hundreds nanometers.
With the continuous scaling down of critical dimension of semiconductor devices, a method for manufacturing transistors with high-k metal gates is adopted in main stream technologies. FIG. 1 to FIG. 4 are schematic cross-sectional views of intermediate structures of the method for manufacturing a transistor in prior art.
Referring to FIG. 1, firstly a plurality of transistors are formed on a substrate 10. Each transistor includes a gate 14 and a spacer 15 on sidewalls of the gate 14. The gate includes polysilicon. Then, a stressed layer 11, a first silicon oxide layer 12 and a second silicon oxide layer 13 are formed successively on the gate 14, the spacer 15 and a part of the substrate 10 which is not covered by the transistors. The stressed layer includes silicon nitride and the first silicon oxide layer 12 is formed by a high aspect ratio polymer (HARP) process which has excellent filling properties. The first oxide layer 12 formed by the HARP process is very soft because no annealing process is performed in the HARP process. The second silicon oxide layer 13 is formed by a TEOS method.
Referring to FIG. 2, bulk silicon oxide is removed by a first chemical mechanical planarization (CMP) process, wherein a part of the second silicon oxide layer 13 is removed in a first CMP process.
Referring to FIG. 3, silicon oxide on the gate 14 and the spacer 15 is removed by a second CMP process. Specifically, in the second CMP process, the second silicon oxide layer 13 and a part of the first silicon oxide layer 12 are removed, the stressed layer 11 is adopted as a stop layer, and the part of the first silicon oxide layer which is located on the stressed layer 11 is removed completely.
Referring to FIG. 4, silicon nitride on the gate 14 is removed by a third CMP process. In the third CMP process, particles of slurry may agglomerate around the gate 14, and the first silicon oxide layer 12 can be easily abraded because the first silicon oxide layer 12 is very soft, which may induce a dishing 17 around the gate 14 and influence on subsequent manufacturing processes. For example, when a CMP process is performed to materials such as aluminum, the aluminum may remain in the dishing 17. The phenomenon of forming a dishing around the gate 14 in the third CMP process is called Fang Issue in semiconductor manufacturing field.
And the Fang Issue has become a pressing problem which should be solved in semiconductor manufacturing field as quickly as possible.